1. Field of the Invention
The present invention relates to the design of decoding systems. More specifically, the present invention pertains to a software decoding system with a mechanism for handling decoding time overruns while sustaining real time output.
2. Related Art
The ever-increasing demand for high quality audio and video media has fueled the advent of audio and video storage and retrieval technology. In particular, one popular set of standards for audio and video compression is the MPEG (Moving Pictures Experts Group) standard. Today, there are several versions of the MPEG standard, each designed for different applications. Specifically, MPEG-2 is designed for high bandwidth applications such as broadcast television, including high definition television (HDTV). In order to listen to and view the content in an MPEG-2 transport stream, a decoding system capable of decoding the compressed audio and video data is essential.
Hardware decoders have been used in most real time MPEG-2 decoding applications due to their speed and because the performance of programmable signal processors has only recently been able to fully support MPEG-2 demultiplexing and decoding. Therefore, a complete software-based decoding system for MPEG-2 was not previously feasible. Now that programmable signal processors can deliver the requisite performance for software-based processing of an MPEG-2 data stream, software-based MPEG-2 decoding systems have been proposed and realized.
A software-based decoding system offers many advantages over hardware decoders. One major advantage is the flexibility that is afforded by a software-based system over a pure hardware-based system. In a hardware decoder, the implementing logic is hard-wired in various hardware components of the decoder. Once fabrication of the hardware components has begun, the hardware layout generally cannot be altered to accommodate any design changes. In contrast, in a software-based system, the software code implementing the functionalities is developed and then loaded into a programmable signal processor. Thus, any last minute changes can be incorporated into the software and loaded into the signal processor without being limited by the manufacturing schedule of the signal processor. With reprogrammable signal processors, it is even possible to reload updated software code into the processor subsequently if that becomes necessary. Such ability to accommodate design changes is highly desirable. Moreover, a software-based decoding system can also be programmed to process various MPEG versions without hardware modifications. As such, there exists a need for a software-based decoding system and method which provides greater flexibility over existing hardware-based MPEG-2 decoders.
An MPEG-2 decoding system generally comprises multiple functional blocks which process a stream of compressed data and system information to generate uncompressed audio and video outputs. More specifically, the functional blocks, such as a demultiplexing block and a decoding block, form a pipeline to process the stream of incoming data. In hardware decoders, each functional block is typically implemented as an independent hardware block. These hardware blocks operate in parallel, with the data being processed moving from one block to the next. Importantly, in such hardware designs with the parallel pipelining as described above, processing time in each block is constant irrespective of the complexity of the incoming data stream. In particular, the processing time in the decoding block is fixed for each and every frame in the incoming data stream regardless of the complexity of the compressed data and system information contained therein.
Like a hardware decoder, a software-based decoding system also comprises multiple functional blocks, or modules, for processing an MPEG-2 data stream, but the modules are implemented with software running on a signal processor. However, unlike the case in a hardware decoder, processing time in each of the software modules of a software-based decoding system is highly dependent upon the complexity of the compressed data and system information in the MPEG-2 data stream. The processing time varies from frame to frame in a software-based decoding system. On the other hand, the display time for each frame remains the same irrespective of the complexity of the frame. This timing discrepancy between processing and display poses a challenge in the implementation of a software-based decoding system due to the potential occurrence of overrun cases.
It is appreciated that there are signal processors that can provide the level of performance necessary to ensure that the processing time of a frame processed by a software decoder never exceeds the display time of that frame. In other words, a high performance processor capable of handling the worst case scenario (e.g., the most complex frame possible in the data stream in question) can be used for implementing a software-based decoding system so that overrun cases are precluded and real time display is guaranteed. However, these high performance processors are typically expensive. Since these decoders will be widely deployed in various end-user appliances, it is highly advantageous to minimize the cost of these decoders and their components. Therefore, it would be advantageous to provide a software-based decoding system which uses an inexpensive processor and yet which can sustain real time display in all circumstances.
A further challenge exists in the implementation of a software-based decoding system. Typical signal processors available on the market today support a single instruction pointer (program counter). A processor of this type performs a single thread of execution at any given time. Consequently, in a software-based decoding system implemented on such a signal processor, the total processing time for a given frame through the various functional modules is cumulative. In other words, the total processing time for a frame is the sum of the processing time in each of the functional software modules for that frame. Thus, for a frame of high complexity, the extra processing time required in each functional modules adds up, thereby presenting a greater timing discrepancy to be overcome in implementing a software-based decoding system. Thus, it would be advantageous to provide a software-based decoding system which uses a processor having a single instruction pointer.